tkgate-data 1.8.7-4 / usr / share / tkgate-1.8.7 / locale / en / messages

#
#   Copyright (C) 1987-2000 by Jeffery P. Hansen
#
#   This program is free software; you can redistribute it and/or modify
#   it under the terms of the GNU General Public License as published by
#   the Free Software Foundation; either version 2 of the License, or
#   (at your option) any later version.
#
#   This program is distributed in the hope that it will be useful,
#   but WITHOUT ANY WARRANTY; without even the implied warranty of
#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#   GNU General Public License for more details.
#
#   You should have received a copy of the GNU General Public License
#   along with this program; if not, write to the Free Software
#   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# Last edit by hansen on Sun Jan 28 20:13:23 2007

##############################################################################
#
# basic strings
#
b.dismiss	Dismiss
b.close		Close
b.ok		OK
b.clear		Clear
b.cancel	Cancel
b.open		Open...
b.bitw		Bit Width
b.in		in
b.out		out
b.inout		inout
b.browse	Browse...
b.label		Label
b.find		Find
b.edit		Edit...
b.add		Add...
b.delete	Delete
b.deleteb	Delete...
b.apply		Apply
b.anchor	Anchor
b.tech		Technology

##############################################################################
# Menu strings
#
file		File
edit		Edit
tool		Tool
simulate	Simulate
module		Module
gate		Gate
make		Make
circ		Circuit

new		New
open		Open...
openlib		Open Library...
save		Save
saveas		Save...
print		Print...
options		Options...
quit		Quit

undo		Undo
redo		Redo
cut		Cut
copy		Copy
paste		Paste
selall		Select All
find		Find...
ccrot		Rotate
cwrot		Back Rotate
algnv		Align Ver.
algnh		Align Horz.
zoomin		Zoom In
zoomout		Zoom Out

move		Move/Connect
delg		Delete Gate
cutw		Cut Wire
inv		Invert
bitw		Bit Width
debug		Debug
rot0		Rot 0
rot90		Rot 90
rot180		Rot 180
rot270		Rot 270

simbegin	Begin Simulation
simend		End Simulation
simadprobe	Add/Delete Probe
simrun		Run
simpause	Pause
simstep		Step Epoch(s)
simcycle	Step Cycle
simbreak	Breakpoint...
simscript	Exec. Script...
simload		Load Memory...
simdump		Dump Memory...

modopen		Open
modclose	Close
modseti		Set Interface
modediti	Edit Interfaces...
modnew		New...
moddel		Delete...
modcopy		Copy...
modrename	Rename...
modclaim	Claim...
circprop	Circuit Properties...
cpath		Critical Path...

gataddin	Add Input
gataddout	Add Output
gataddinout	Add BiDir
gatiochg	Change Type
gatanchor	Anchor Selected
gatunanchor	Unanchor Selected
gatprop		Properties...
gatrep		Replicate
gatdel		Delete
gatsettech	Set Technology

gmswitch	I/O
gmgate		Gate
gmredgate	Reduction
gmmsi		MSI
gmalu		ALU
gmmem		Memory
gmmod		Module
gmcomment	Comment
gmframe		Frame

gmxswitch	Switch
gmdip		DIP Switch
gmground	Ground
gmvdd		Vdd
gmmerge		Wire Merge
gmclock		Clock

gm.led		LED
gm.ledbar	LED Bar
gm.ledhex	7-Seg. LED (HEX)
gm.leddec	7-Seg. LED (DEC)
gm.ledseg	7-Seg. LED (Direct)

gmtty		TTY

gmand		AND
gmnand		NAND
gmor		OR
gmnor		NOR
gmxor		XOR
gmxnor		XNOR
gmbuf		Buffer
gminv		Inverter
gmtribuf	Tri-Buffer
gmnmos		NMOS
gmpmos		PMOS

gmrand		AND
gmrnand		NAND
gmror		OR
gmrnor		NOR
gmrxor		XOR
gmrxnor		XNOR

gmadd		Adder
gmmult		Multiplier
gmdiv		Divider
gmlshift	Left Shift
gmrshift	Right Shift
gmarshift	Arith. Right Shift
gmroll		Roll

gmreg		Register
gmff		Flip-Flop
gmrff		Rev. Flip-Flop
gmram		RAM
gmrom		ROM

gm21mux		2-1 Multiplexor
gm41mux		4-1 Multiplexor
gm81mux		8-1 Multiplexor
gm12dec		1-2 Decoder
gm14dec		1-4 Decoder
gm18dec		1-8 Decoder
    
gmmodinst	Module Instance
gmmodin		Module Input
gmmodout	Module Output
gmmodinout	Module InOut

addwireseg	Add Wire Segment

help		Help
hlpabout	About...
hlplicense	License...
hlpdoc		Documentation...
hlptut		Tutorials
hlpexample	Examples
exampcomb	Combinational Logic
examp3bit	3-Bit Counter
examp8bit	8-Bit Counter
examptrff	Transistor-Level FF
exampcpu	Menagerie CPU
tutwelcome	TkGate Intro
tutcreate	Creating a Circuit
tutedit1	Editing a Circuit (1)
tutedit2	Editing a Circuit (2)
tutmods		Using Modules
tutsim		Simulating a Circuit

# Scope Menu
menu.sc.prtrace	Print Trace...
menu.sc.close	Close
menu.sc.trace	Trace
menu.sc.zoomin	Zoom In
menu.sc.zoomout	Zoom Out

scope.emptymsg	Double-click on a wire to add or delete a trace.
comment.empty	[Double click to add text.]
##############################################################################
# Interface strings
#
ifile		File
imodule		Module
iblmodule	Modules
iports		Ports
ibits		Bits:

#############################################################################
#
# Mux/demux options
#
db.gate.mux.dataorder	Input Ordering
db.gate.mux.ord1.hdr	Left-to-Right
db.gate.mux.ord2.hdr	Right-to-Left
db.gate.mux.ord1.exp	-begin-
Order MUX inputs from left to right.
-end-
db.gate.mux.ord2.exp	-begin-
Order MUX inputs from right to left.
-end-

db.gate.demux.dataorder	Output Ordering
db.gate.demux.ord1.hdr	Left-to-Right
db.gate.demux.ord2.hdr	Right-to-Left
db.gate.demux.ord1.exp	-begin-
Order DEMUX outputs from left to right.
-end-
db.gate.demux.ord2.exp	-begin-
Order DEMUX outputs from right to left.
-end-

db.gate.mux.select	Selector Style
db.gate.mux.sel1.hdr	Selector on Left
db.gate.mux.sel2.hdr	Selector on Right
db.gate.mux.sel1.exp	-begin-
Place the data selector on the left side of
the gate.
-end-
db.gate.mux.sel2.exp	-begin-
Place the data selector on the right side of
the gate.
-end-

db.gate.demux.select	Selector Style
db.gate.demux.sel1.hdr	Selector on Left
db.gate.demux.sel2.hdr	Selector on Right
db.gate.demux.sel1.exp	-begin-
Place the data selector on the left side of
the gate.
-end-

db.gate.demux.sel2.exp	-begin-
Place the data selector on the right side of
the gate.
-end-

db.gate.fftype		Flip-Flop Orientation 
db.gate.ffnormal.hdr	Normal
db.gate.ffnormal.exp	-begin-
Flip-Flop with data
flowing left to right.
-end-

db.gate.ffreverse.hdr	Reversed
db.gate.ffreverse.exp	-begin-
Flip-Flop with data
flowing right to left.
-end-

#############################################################################
#
# LED types
#
db.gate.led.type	LED Type
db.gate.led.bit.hdr	Bit
db.gate.led.bar.hdr	Bar Graph
db.gate.led.hex.hdr	7-Segment (HEX)
db.gate.led.dec.hdr	7-Segment (DEC)
db.gate.led.seg.hdr	7-Segment (Direct)

db.gate.led.bit.exp	-begin-
Single-lamp LED display
for 1-bit signals.
-end-
db.gate.led.bar.exp	-begin-
LED bar graph with
one bar per bit.
-end-
db.gate.led.hex.exp	-begin-
Display signal in
hexidecimal.
-end-
db.gate.led.dec.exp	-begin-
Display signal in
decimal.
-end-
db.gate.led.seg.exp	-begin-
Signal bits directly
control LED segments.
-end-

#############################################################################
# Net Dialog Box
#
db.net.name	Net Name
db.net.hide	Hide Name
db.net.bits	Bit Width	
db.net.port	Port Type
db.net.in	in
db.net.out	out
db.net.inout	inout
db.net.inets	Nets

##############################################################################
# Gate dialog box
#
db.gate.signam		Signal Name
db.gate.portnam		Port Name
db.gate.iotype		Type
db.gate.bitw		Bit Width
db.gate.cyclew		Cycle Width
db.gate.phase		Phase
db.gate.duty		Duty
db.gate.port		Port
db.gate.bitws		Bits
db.gate.gtype		Gate Type
db.gate.gname		Gate Name
db.gate.hidenam		Hide Name
db.gate.anchor		Anchor
db.gate.cpbreak		Critical Path Partition
db.gate.butstate	Button State
db.gate.dipval		Switch Value
db.gate.memfilenam	Memory File
db.gate.modname		Function
db.gate.islink		Text is Hyperlink
db.gate.link		Link to File
db.gate.findw		Search for wires only
db.gate.findg		Search for gates only
db.gate.findwg		Search for wires and gates
db.gate.general		General
db.gate.details		Details
db.gate.ports		Port
db.gate.delay		Delay
db.gate.stddelay	Standard Delay
db.gate.custdelay	Custom Delay
db.gate.extbar		Use extender bars

db.led.type		LED Type
db.led.bit		Bit
db.led.bar		Bar Graph
db.led.hex		7-Segment (HEX)
db.led.dec		7-Segment (DEC)
db.led.seg		7-Segment (Direct)

cpath.cloops -begin-
Combinational loops were detected in your circuit.
In order to do delay analysis on this circuit, you
must either break the loop, or mark some of the
gates in the loop as a "Critical Path Partition"
point.  Nets at which a loop was detected are
listed below.
-end-

##############################################################################
# Print dialog box
#
print.outto		Output to
print.printer		Printer
print.file		File
print.prcmd		Print Command
print.filename		File Name
print.epssave		Save as Encapsulated Postscript.
print.doctit		Document Title
print.prmod		Print Modules
print.epcm		Epochs/cm
print.estpg		Estimated pages
print.all		All
print.cur		Current
print.use		Used
print.sel		Selected
print.inclib		Include library modules.
print.papsz		Paper Size
print.orient		Orientation
print.portrait		Portrait
print.landscape		Landscape
print.2side		Print Double-Sided
print.opts		Options
print.scale		Scale large modules to fit page.
print.partition		Partition large modules into multiple pages.
print.incidx		Include index.
print.incgraph		Include hierarchy graph.
print.4up		Print small modules four per page.
print.range		Range Selection
print.fulltr		Full Trace
print.parttr		Partial Trace
print.start		Start
print.end		End

##############################################################################
#
# Options dialog
#
opt.site		Site Name
opt.inst		Instances
opt.mods		Modules
opt.modports		Module Ports
opt.frames		Frames
opt.comment		Comments
opt.hlink		Hyperlinks
opt.wire		Single-Bit Wires
opt.bus			Multi-Bit Wires
opt.tools		Gate Tools
opt.cpath		Critical Path
opt.grid		Scope Grid
opt.logic1		Logic One
opt.logic0		Logic Zero
opt.float		Float
opt.unknown		Unknown/Conflict
opt.offled		Off LED
opt.onled		On LED
opt.zled		Floating LED
opt.restdef		Restore Defaults
opt.regudate		Region Update
opt.smoothscroll	Smooth Scrolling
opt.outmove		Outline Move modules
opt.balloon		Enable Help Balloons
opt.debug		Enable Debugging
opt.novice		Novice Mode
opt.ckpoint		Do Checkpointing
opt.freq		Interval
opt.beak		Enable Special Modes
opt.mode		Mode
opt.normal		Normal
opt.bat			Bat
opt.trek		Star Trek
opt.miles		Miles
opt.contver		Automatic Integrity Checking
opt.showsimcmd		Display Simulator Stream
opt.logfile		Simulator Log File
opt.estepsz		Epoch Step Size
opt.cstepsz		Clock Cycle Step Size
opt.overstep		Clock Overstep
opt.sorttraces		Sort traces alphabetically on scope
opt.rememberprobes	Remember Probe Placement
opt.vpopupdelay		Value Pop-Up Delay
opt.initscript		Initialization script
opt.posedge		Clock step stops on all clock posedges
opt.setclock		Clock step stops on clock
opt.delayfilepath	Delay Files
opt.general		General
opt.print		Print
opt.simulate		Simulate
opt.analysis		Analysis
opt.color		Color
opt.undolen		Max Undo

opt.cpopts		Critical Path Options:
opt.maxpath		Maximum Number of Paths:
opt.cpflash		Display with Flashing Path

opt.vercheck		-begin-
Periodically check for new versions of tkgate over
the Internet.  Do not enable unless you have continuous
access to the Internet.
-end-

##############################################################################
#
# Block list dialog boxes
blklst.newmod		New Module 
blklst.delmod		Delete Module
blklst.frommod		Copy Module From
blklst.tomod		To
blklst.oldname		Old Name
blklst.newname		New Name
blklst.claim		Claim Module

##############################################################################
#
# Circuit Dialog box
#
circ.topmod		Top-Level Module
circ.discchg		Discard Changes
circ.iniscript		Initialization Scripts
circ.noscript		No script files selected.
circ.really1		Do you really want to remove
circ.really2		from the list of initialization scripts
circ.extbar		Use Extender Bars

##############################################################################
# Simulator
#
sim.breakpt		Breakpoint

##############################################################################
#
# Command box
#
cmd.file		File Name
cmd.topname		Top Module Name

##############################################################################
#
# Critical path messages
#
cp.delay		Path Delay:
cp.pathl		Path List:
cp.numpath		Number of Paths:
cp.recompute		Recompute

##############################################################################
# Error messages
#
err.verilog		Errors in file:
err.nopin		Can't change selected pin.
err.badhex		Illegal hex value '%s' ignored.
err.gatanchor		Gate(s) are anchored and can not be moved.
err.libmode		Illegal operation on library module (convert to normal module to edit).
err.badfind		Can't find target '%s'.
err.badopendel		Can't delete open module.
err.nosrcmod		Source module '%s' not found.
err.noerr		Can not locate error.
err.misserr		Error information incomplete (did the simulator crash?)
err.pounimpl		Unimplemented error in ParseOption

err.badinadd		Can't add any more inputs to selected gate.
err.badoutadd		Can't add any more outputs to selected gate.
err.badinoutadd		Can't add any more inout pins to selected gate.
err.badpinchg		Can't change pin types on selected gate.
err.badnetname		Illegal characters in identifier deleted.
err.netbcrename		Identifier renamed to '%s' because of illegal characters.
err.netconfnet		Identifier renamed to '%s' because of conflict.
err.netconfgat		Identifier renamed to avoid conflict with primitive gate name
err.netconfkw		Identifier renamed to avoid conflict with reserved word.
err.badconsame		Connection refused because wires are part of the same net.
err.badconptsp		Connection refused because both wires are module ports or supply.
err.badconbitw		Connection refused because bit widths do not match.
err.badrange		Non-positive range for scope trace is not allowed.
err.badlprcmd		Unable to exectute printer command '%s'.
err.badpsopen		Unable to open file '%s' for postscript output.
err.badid		Illegal identifier '%s'.

err.bkpt.badexp		Syntax error in breakpoint expression.  Must be one of: 'net', '!net', 'net==value', 'net!=value'
err.bkpt.badnet		Invalid net name '%s'. Names must start with a letter and contain only letters, digits and '.'.
err.bkpt.badval		Syntax error in value '%s'.  Must be decimal or verilog-style constant.
err.bkpt.toomany	Too many breakpoints.  Maximum is %d.

err.sim.badtmp		Could not save temporary file '%s' for simulator (disc full?)
err.sim.syntx		Syntax error in '%s' command.
err.sim.noincl		Include file '%s' not found.
err.sim.clockbadedge	Illegal edge indicator '%c' in clock command.
err.sim.nobkpt		No such breakpoint '%s'.
err.sim.nonet		Can't find net '%s'.
err.sim.nogate		Can't find gate '%s'.
err.sim.badbin		Illegal charcter in binary constant '%s'.
err.sim.notswitch	Gate '%s' is not a switch, dip or register.
err.sim.badcmd		Unrecognized command '%s' in simulation script.

err.noteditpchg		Properties can only be changed in edit mode.	
err.badeditop		Illegal interface edit mode operation.
err.badopen		Unable to open input file '%s'.
err.badlibopen		Unable to open library file '%s'.

err.nomark		Please set a mark with the left mouse button before selecting a gate type.
err.badgate		Unknown gate type.
err.badmake		Unable to create gate.

err.badportadd		Can't add ports to gates of this type.
err.badportdel		Selected port can not be deleted.
err.badportedit		Selected port can not be edited.
err.noport		No port selected.

err.manypages		-begin-
There are an awful lot of
pages in this document.  Are
you sure you want to print it?
-end-

err.nojump		-begin-
The 'jump-to-module' feature can not be used
in simulation or critical path analysis mode.
Please navigate manully to the target block
by selecting modules and opening them with the
'>' keyboard command.  You can leave a module
you are in with the '<' keyboard command.
-end-

err.nomod		Module '%s' is not defined.
err.modlock		Logic Block is Locked!
err.closeroot		Can't close top-level module.  Use quit.
err.sim.isrun		Simulator is already running (Use 'Ctrl-s e' to end).
err.sim.isnotrun	Simulator is not running (Use 'Ctrl-s b' to start).
err.editonly		Command not valid when in simulation mode.
err.simonly		Command valid only in simulation mode.

err.norotation		Selection can not be rotated due to attaching wires.

err.nodel		No deletable selection.
err.modnotdef		Module '%s' is undefined.
err.moddef		The block '%s' already exists.
err.noprop		Selected gate has no editable properites.
err.openscript		Can't open simulation script file '%s'
err.oldversion		Loaded file with obsolete version number %s (current version is %s).
err.futureversion	Loaded file saved by future tkgate version %s (this version is %s).
err.badversion		Unknown version number.  Use at your own risk.
err.nodrive		Net %s has no driver in module %s.
err.noconn		Wire %s{%d} has no connections - deleted.
err.oldportact		Please right click on port or module edge to add/change port.

err.backupfail		Unable to create backup file '%s'.

err.corruptnewsave	-begin-
TkGate was able to save your file in '%s', but it appears
to be corrupted.  If you have checkpointing enabled try
loading one of the checkpoint files.  Use 'tkgate -V' to
check the integrety of a save file.
-end-

err.corruptsave		-begin-
TkGate detetected a problem while trying to save the file '%s'.
The existing file has been left unmodified and the damaged file has
been written to '%s'.  If you have checkpointing enabled you
can try loading one of the checkpoint files.  You can also use
'tkgate -V' to check the integrety of a save file.
-end-

err.badsave		-begin-
A problem has occured trying to open or write the file '%s'.  Check
file/directory protections and or disk space.
-end-

err.nosafesave		-begin-
A problem has occured attempting to save '%s'.  If you wish, you can
try again without save validation.  If you say "no", the original file
will remain unmodified.  If you say "yes" the original file will be
overwritten, but may be destroyed if a problem occurs.  Would you like
to attempt an unvalidated save?
-end-

err.noback		-begin-
File was created by tkgate
%s, and may not be readable
by versions earlier than
current version (%s) if you
save.
-end-

##############################################################################
# Informational messages
#
msg.selwire		Selected wire named '%s'.
msg.selgate		Selected %s named '%s'.
msg.selblock		Selected %s block named '%s'.
msg.modoverwt		Destination module '%s' already exists.  Overwrite?
msg.foundgate		Found gate named '%s'.
msg.foundwire		Found wire named '%s'.
msg.searchagn		Target string '%s' not found.  Hit 'find' to restart search again.
msg.sim.chgtoroot	Simulation mode requires root module at top of edit stack.
msg.sim.nogatemod	Simulation mode requires concrete module stack.
msg.setinterface	Set module interface for '%s'.
msg.needsel		Please select a module instance.
msg.wroteckpt		Checkpointed to %s...
msg.save		Saved circuit to '%s'.
msg.reallynew		Circuit has been modified.  Do you really want to discard your changes and create a new circuit?
msg.reallyquit		Circuit has been modified.  Do you really want to exit?
msg.notlib		Module '%s' is not a library module.

##############################################################################
# Miles messages (Activated when Miles Bader uses tkgate)
#
miles.msg1		Only a fool would put %s%s there, Miles.
miles.msg2		That's a really stupid place to put %s%s, Miles.
miles.msg3		That's a terrible place for %s%s, Miles.
miles.msg4		Miles, you are a fool for putting %s%s there.
miles.msg5		Only you would put %s%s there, Miles.
miles.msg6		Putting %s%s there is proof of your absolute stupidity, Miles.
miles.msg7		Why don't you give up Miles, this is a stupid circuit.
miles.msg8a		It's pointless to continue, Miles.
miles.msg8b		It's obvious you can't design a circuit


##############################################################################
# Balloon Help
#

ho.new		-begin-
Clear the current circuit,
and start editing a new one.
-end-

ho.open		Open a circuit from a file.
ho.save		Save circuit to current file.
ho.print	Print current circuit.

ho.move		-begin-
Move/Connect - By clicking and dragging you can:
  Set the position for a new gate
  Move gates and wires
  Connect wires
By double-clicking you can:
  Edit gate, wire and port properties
  Edit comment text
-end-

ho.delgat	-begin-
Delete Gate - Use this
tool to delete gates.
-end-

ho.cutw		-begin-
Cut Wire - Use this
tool to cut wires.
-end-

ho.inv		-begin-
Invert - Use this tool to add
or remove inverters from gate ports.
-end-

ho.bitw		-begin-
Bit Width - Use this tool to change the
bit size of a wire.  Enter the number of
bits in the entry box in the lower right
corner of the window.
-end-

ho.currot	-begin-
Change the default
rotation for newly
created gates.
-end-

ho.ccrot	-begin-
Rotate the currently 
selected gate(s) counter-
clockwise. 
-end-

ho.cwrot	-begin-
Rotate the currently 
selected gate(s) clockwise. 
-end-

ho.modopen	Open the selected module.
ho.modclose	Close the current module.

ho.undo	Undo previous action(s)
ho.redo	Redo undone action(s)

ho.simstart	-begin-
Start the simulator, open the logic analyzer
and execute any initialization scripts if defined.
-end-

ho.simgo	-begin-
Run simulator in continuous execution mode.
Note that combinational circuits simulate
only until the circuit reaches steady state.
-end-

ho.simpause	-begin-
Pause a continuously running simulation.
-end-

ho.simstep	-begin-
Step a fixed interval of time.
Open the simulation options
window to set the step size.
-end-

ho.simclock	-begin-
Step a fixed number of clock
cycles.  Open the simulation options
window to set the step size.
-end-

ho.simstop	-begin-
End the current simulation
and return to edit mode.
-end-

ho.simbreak	-begin-
Edit the current breakpoints.  Simulation
will be halted when a breakpoint condition
becomes true.
-end-

ho.simexec	Execute a simultion script.

ho.simload	-begin-
Load memory with contents of
a .mem file.
-end-

ho.simdump	-begin-
Dump the contents of a memory
to a .mem file.
-end-

ho.sim.break	-begin-
Enter a simulator breakpoint.  Breakpoints are expressions
which cause the simulator to pause execution when they become
true.  Currently only simple expressions with a single
relational operator such as "w1 == 0" or "w7 != 8" are
supported.  Expressions such as "w8" or "!w2" may also be
used to test for non-zero and zero values respectively.
-end-

ho.f.modlist	-begin-
List of all modules currently loaded.
The top-level module is indicated by
a trailing "+", and library modules are
shown in parentheses.
-end-

ho.netlist	-begin-
List of nets in the current module.
 Nets marked with a '@' have hidden
names.  Multi-bit nets are displayed
with a range after them.
-end-

ho.ports	-begin-
List of ports on the current
module. A '>' indicates an input,
a '<' indicates an output, and a
'=' indicates an inout."
-end-

ho.status.logo		-begin-
Simulation status indicator.  If the iron gate
logo is shown, tkgate is in edit mode.  If the
quadrapedal AND gate is shown, tkgate is in
simulation mode.  If the AND gate is stationary,
the simulation is paused, and if it is walking
the simulation is running.
-end-

ho.status.msg		Messages from tkgate are displayed here.

ho.status.block		The stack of modules being edited.

ho.status.file		-begin-
The current file being edited.  A '*' indicates
that the buffer has been modifed since
the last save.
-end-

ho.print.selall		Print all modules currently loaded by TKGate.
ho.print.selcur		Print only the current module in the TKGate edit window.
ho.print.seluse		-begin-
Print all modules "in use". In use modues are 
those that are a decendent of the root module.
-end-

ho.print.fulltrace	Print the entire trace.

ho.print.parttrace	-begin-
Print a portion of the trace.  Enter the starting
and stopping times in the entry windows below, or
use the right mouse button to select a range on the
scope window (use shift-right to select long ranges).
-end-

ho.print.parttracestart	Starting time of trace output.
ho.print.parttraceend	Ending time of trace output.


ho.print.selsel		-begin-
Print only the modules selected below.  Use
the control key to select multiple modules.
-end-

ho.print.modlist	Select the modules to be printed.

ho.circuit.discchg	-begin-
TkGate will not display a warning if you
discard changes without saving.
-end-

ho.circuit.extbar	-begin-
Basic gates (AND, OR, XOR) will use
extender bars to handle many input
gates.
-end-

ho.cmd.bitw		-begin-
Wires selected with the cursor
will be set to this bit width.
-end-

ho.edgat.extbar		-begin-
If selected, multi-input basic gates
will use extender bars as inputs
are added to the gate.
-end-

ho.edgat.signam		-begin-
The name of the selected signal on the
selected gate.  You can change the name
of the signal by editing it here.
-end-

ho.edgat.port		-begin-
The name of the port for this signal
on the gate.  This field can only be
edited for module instances.
-end-

ho.edgat.iolab		-begin-
The direction of the selected signal
on the selected gate.  This field can only
be edited for module instances.
-end-

ho.edgat.bitlab		-begin-
The bit width of the selected signal
on the selected gate.  You can change the
bitwidth by editing it here.
-end-

ho.edgat.cycle		The total number of epochs in a clock cycle.
ho.edgat.phase		The starting point of the cycle (in percent).
ho.edgat.duty		The percent of the cycle, the clock is low.

ho.edgat.cname		Name of connected net.
ho.edgat.cport		Port to which net is connected.
ho.edgat.ctype		Type of connection.
ho.edgat.cbitw		Bit width of connected net.
ho.edgat.cedit		Edit the selected port.
ho.edgat.cadd		Add a port.
ho.edgat.cdel		Delete the selected port.

ho.edgat.hide		-begin-
Set this flag to disable
display of gate name.
-end-

ho.edgat.gtype		Type of the gate.
ho.edgat.gname		Name of this gate instance.
ho.edgat.ganchor	Set this flag to anchor the position of a gate.
ho.edgat.gx		X coordinate of gate.
ho.edgat.gy		Y coordinate of gate.

ho.edgat.swstate	-begin-
The initial state of the switch to use when
starting a simulation.
-end-

ho.edgat.dipstate	-begin-
The initial state of the dip switch to use
when starting a simulation.
-end-

ho.edgat.range		The range of bits to pull off a bus.

ho.edgat.memfile	-begin-
The file with the initial state for this memory.
This file is read when the simulator is started.
-end-

ho.edgat.func		The function type of this module.
ho.edgat.frame		The frame label.

ho.traceprint		Print logic trace. 

ho.showxhair		-begin-
If this button is depressed, a vertical crosshair
line will be displayed in the scope window.
-end-

ho.opt.sorttraces	-begin-
If this option is enabled, traces on the
scope window will be displayed in sorted
order.  If this option is disabled, traces
on the scope window will be displayed in
the order in which the probes were set.
-end-

ho.opt.rememberprobes	-begin-
If this option is enabled, any probes set
while in simulation mode will be remembered
and automatically added when restarting the
simulation.
-end-


ho.opt.undolen		-begin-
Maximum number of undo actions to retain.
-end-

ho.opt.site		-begin-
The name of the site where tkgate is
installed.  This name will be used on
any printer or postscript output.
-end-

ho.opt.smooth		-begin-
If this option is enabled, scrolling will
be optimized by using bitmap copies instead
of a complete redisplay.  You can turn this
off if there are any problems with your server.
-end-

ho.opt.clip		-begin-
If this option is enabled, clipping will be
used to update only the exposed portion of
the window on a redisplay.  Otherwise the
entire display will be redrawn for all
exposures.
-end-

ho.opt.outmove		-begin-
If this option is enabled, only an outline
of module instances being moved will be displayed
while dragging.  Use this feature only on machines
with slow displays.
-end-

ho.opt.bhelp		-begin-
If this option is enabled,  help balloons will 
be activated.  Help balloons, such as this one,
provide tips on interface elements when the
mouse is over them.
-end-

ho.opt.novice		-begin-
If no other circuit is specified on the command
line.  A TkGate tutorial will be disaplyed as
the initial circuit on start up.
-end-

ho.opt.debug		-begin-
Enables several debugging features
only useful to TkGate developers.
-end-

ho.opt.ckpt		Enable checkpointing of unsaved circuits.
ho.opt.ckptfreq		Frequency of checkpoints in seconds.

ho.opt.beak		-begin-
Enable these totally useless features.
If you disable this feature, these modes
(and this checkbox) will no longer appear
in the options box.  The only way to
reenable them will be to edit
your .tkgate-preferences file.
-end-

ho.opt.miles		-begin-
If this mode is enabled, TkGate will
periodically insult the intelligence of
the user.
-end-

ho.opt.bat		-begin-
If this mode is enabled, TkGate will
set up an enviornment for designing a
bat computer.
-end-

ho.opt.trek		Beam me up Scoty!
ho.opt.normal		Disable fun Stuff.

ho.opt.simstep		-begin-
The number of epochs to advance when
the step command is issued.
-end-

ho.opt.ckstep		-begin-
The number of clock cycles to advance
when the clock step command is issued.
-end-

ho.opt.ckover		-begin-
The number of epochs past rising edge
of the clock to advance when the clock
step command is issued.
-end-

ho.opt.vpopupdelay		-begin-
The delay in milliseconds between pressing
and holding the mouse button and the display
of a signal value.  On some systems, short
delay values interfere with the ability to
recognize a double click.  If you have this
problem, increase this value.  Values between
1 and 10000 are allowed.
-end-

ho.opt.init		-begin-
A simulation script file to execute
automatically when the simulation
is started.
-end-

ho.opt.ckall		-begin-
If this mode is enabled, the clock step
command will pause the simulation on the
positive edge of any clock in the circuit.
-end-

ho.opt.ckspec		-begin-
If this mode is enabled, the clock step
command will pause the simulation only on
the positive edge of the specified clock.
-end-

ho.deftech		-begin-
Default technology for new gates.
Affects delay of gates. To change
the technology of a specific gate,
open its properties box (double
click) and select the "Delay" tab.
-end-

ho.techbut		-begin-
Use delays from standard technology
definition file.  To add custom
technologies, add them to the list
in the "File -> Options -> Simulate"
menu.
-end-

ho.custbut		-begin-
Set custom delay values for this gate.
-end-

ho.contver		-begin-
Continuously verify the integrity of internal
data structures after every operation.
-end-

ho.simwatch		-begin-
Display commands sent between
the GUI and the simulator.
-end-

ho.simlog		-begin-
Write commands issued to the
simulator to a log file.  The
log file can then be used as
input to the simulator in a
debugger.
-end-

ho.cpathanal		-begin-
Find critical paths in a circuit.
-end-